Posted versions here are for personal use only. Copyright is maintained by the authors as well as other copyright holders. Also, please refer to the CV for the most updated publication list.

Books


  1. N. Jha and D. Chen, editors, Nanoelectronic Circuit Design, Springer Publishers, 2011. Get a copy.

Monographs


  1. D. Chen, J. Cong, and P. Pan, FPGA Design Automation: A Survey, Foundations and Trends in Electronic Design Automation, NOW Publishers, 137 pages, November 2006.

  2. Daisuke Mashima, Yao Chen, Muhammad M. Roomi, Subhash Lakshminarayana, and Deming Chen, Cybersecurity for Modern Smart Grid against Emerging Threats, Foundations and Trends in Privacy and Security, NOW Publishers, 100 pages, December 2023.

Book Chapters


  1. D. Chen, Chapter 38: Design Automation for Microelectronics, In Handbook of Automation, edited by Shimon Y. Nof, Springer Publishers, August 2009.

  2. S. Chilstedt, C. Dong, and D. Chen, Carbon Nanomaterial Transistors and Circuits, In Transistors: Types, Materials, and Applications, edited by Benjamin M. Fitzgerald, Nova Science Publishers, 2010.

  3. C. Dong, S. Chilstedt, and D. Chen, FPCNA: a Carbon Nanotube-Based Programmable Architecture, In Nanoelectronic Circuit Design, edited by Niraj Jha and Deming Chen, Springer Publishers, 2011.

  4. W. Zuo, S. Gurumani, K. Rupnow, and D. Chen, “New Solutions for Cross-Layer System-Level and High-Level Synthesis,” In Emerging Technology and Architecture for Big-data Analytics, Springer Publishers, 2017.

  5. S. T. Choden Konigsmark, Wei Ren, Martin D. F. Wong, and Deming Chen, “High-level Synthesis for Minimizing Power Side-Channel Information Leakage,” In Behavioral Synthesis for Hardware Security, Springer Publishers, 2020.

  6. Yun Heo, Gowthami Manikandan, Anand Ramachandran, and Deming Chen. Comprehensive Evaluation of Error-Correction Methodologies for Genome Sequencing Data. In Bioinformatics. Nakaya H (Ed). Exon Publications, Brisbane, Australia. ISBN: 978-0-6450017-1-6. [In Press]

  7. Xiaofan Zhang, Yao Chen, Cong Hao, Sitao Huang, Yuhong Li, and Deming Chen, “Compilation and Optimizations for Efficient Machine Learning on Embedded Systems,” In Embedded Machine Learning for Cyber-Physical, IoT, and Edge Computing, Springer Nature. To Appear.

JOURNAL PAPERS


  1. Hyegang Jun, Hanchen Ye, Hyunmin Jeong, and Deming Chen, “AutoScaleDSE: A Scalable Design Space Exploration Engine for High-Level Synthesis,” ACM Transactions on Reconfigurable Technology and Systems, Volume 16, Issue 3, Article No.: 46, pp 1–30, June 2023.

  2. Jianwei Zheng, Yu Liu, Xuejiao Liu, Luhong Liang, Deming Chen, and Kwang-Ting Cheng, “ReAAP: A Reconfigurable and Algorithm-Oriented Array Processor with Compiler-Architecture Co-Design,” IEEE Transactions on Computers, Volume: 71, Issue: 12, Page(s): 3088-3100, December 2022. (Featured story at IEEE Spectrum: Deep Learning Gets a Boost From New Reconfigurable Processor)

  3. Xinyu Chen, Feng Cheng, Hongshi Tan, Yao Chen, Bingsheng He, Weng-Fai Wong, and Deming Chen, “ThunderGP: Resource-Efficient Graph Processing Framework on FPGAs with HLS,” ACM Transactions on Reconfigurable Technology and Systems, Volume 15, Issue 4, Article No.: 44, pp 1–31, December 2022.

  4. Ashutosh Dhar, Edward Richter, Mang Yu, Wei Zuo, Xiaohao Wang, Nam Sung Kim, and Deming Chen, “DML: Dynamic Partial Reconfiguration with Scalable Task Scheduling for Multi-Applications on FPGAs”, IEEE Transactions on Computers, Volume: 71, Issue: 10, Page(s): 2577 – 2591, October 2022.

  5. Xiaofan Zhang, Yuhong Li, Junhao Pan, and Deming Chen, “Algorithm/Accelerator Co-Design and Co-Search for Edge AI”, IEEE Transactions on Circuits and Systems II, Volume: 69, Issue: 7, Page(s): 3064 - 3070, July 2022.

  6. Xiaofan Zhang, Yuan Ma, Jinjun Xiong, Wen-mei Hwu, Volodymyr Kindratenko, and Deming Chen, “Exploring HW/SW Co-Design for Video Analysis on CPU-FPGA Heterogeneous Systems”, Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume: 41, Issue: 6, Page(s): 1606 – 1619, June 2022.

  7. Sitao Huang, Kun Wu, Hyunmin Jeong, Chengyue Wang, Deming Chen, and Wen-Mei Hwu, “PyLog: An Algorithm-Centric Python-Based FPGA Programming and Synthesis Flow,” IEEE Transactions on Computers, Vol. 70, No. 12, December 2021.

  8. Anand Ramachandran, Steven Lumetta, Eric Klee, and Deming Chen, “HELLO: Improved Neural Network Architectures and Methodologies for Small Variant Calling”, BMC Bioinformatics, 22, Article number: 404, 2021.

  9. Prakhar Ganesh, Yao Chen, Xin Lou, Mohammad Ali Khan, Yin Yang, Hassan Sajjad, Preslav Nakov, Deming Chen, and Marianne Winslett, “Compressing Large-Scale Transformer-Based Models: A Case Study on BERT,” ACL Transactions of the Association for Computational Linguistics, 9: 1061–1080, 2021.

  10. Jianwei Zheng, Chao Lu, Cong Hao, Deming Chen, and Donghui Guo, “Improving the Generalization Ability of Deep Neural Networks for Cross-Domain Visual Recognition," IEEE Transactions on Cognitive and Developmental Systems, Volume: 13, Issue: 3, Page(s): 607 – 620, September 2021.

  11. Cong Hao, Jordan Dotzel, Jinjun Xiong, Luca Benini, Zhiru Zhang, and Deming Chen, “Enabling Design Methodologies and Future Trends for Edge AI: Specialization and Co-design”, IEEE Design & Test, pp 7-26, Volume: 38, Issue: 4, Aug. 2021. Available at https://arxiv.org/abs/2103.15750.

  12. Prakhar Ganesh, Xin Lou, Yao Chen, Rui Tan, David K.Y. Yau, Deming Chen, and Marianne Winslett, “Learning-based Simultaneous Detection and Characterization of Time Delay Attack in Cyber-Physical Systems”, IEEE Transactions on Smart Grid, Page(s): 3581 – 3593, Volume: 12, Issue: 4, July 2021.

  13. Qin Li, Xiaofan Zhang, Jinjun Xiong, Wen-mei Hwu, and Deming Chen, “Efficient Methods for Mapping Neural Machine Translator on FPGAs”, IEEE Transactions on Parallel and Distributed Systems, Page(s): 1866 – 1877, Vol: 32, Issue: 7, July 2021.

  14. Cheng Gong, Yao Chen, Ye Lu, Tao Li, Cong Hao, and Deming Chen, “VecQ: Minimal Loss DNN Model Compression with Vectorized Weight Quantization,” IEEE Transactions on Computers, pp. 696-710, Vol. 70, May 2021.

  15. Liqiang Lu, Size Zheng, Qingcheng Xiao, Deming Chen, and Yun Liang, “Accelerating Convolutional Neural Networks on FPGAs”, SCIENTIA SINICA Informationis, Volume 49, Issue 3, 277-294, March 2019.

  16. Yi Liang, Di He, Hao Zhu, and Deming Chen, “Optimal Blocking Device Placement for Geomagnetic Disturbance Mitigation,” IEEE Transactions on Power Delivery, Volume: 34, Issue: 6, Page(s): 2219 – 2231, December 2019.

  17. K. Campbell, D. Lin, L. He, L. Yang, S. Gurumani, K. Rupnow, S. Mitra, and D. Chen, “Hybrid Quick Error Detection: Validation and Debug of SoCs through High-Level Synthesis,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume: 38, Issue: 7, Page(s): 1345 - 1358, July 2019.

  18. Keith Campbell, Chen-Hsuan Lin, and Deming Chen, “Cost-Effective Error Detection through Mersenne Modulo Shadow Datapaths,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume: 38, Issue: 6, Page(s): 1056 - 1069, June 2019.

  19. Subho Banerjee, Mohamed El-Hadedy, Jong Bin Lim, Zbigniew Kalbarczyk, Deming Chen, Steve Lumetta, and Ravishankar Iyer, “ASAP: Accelerated Short-Read Alignment on Programmable Hardware,” IEEE Transactions on Computers, Volume: 68, Issue: 3, Page(s): 331 - 346, March 2019.

  20. Jianwei Zheng, Chao Lu, Jiefeng Guo, Deming Chen, and Donghui Guo, “A Hardware-Efficient Block Matching Algorithm and Its Hardware Design for Variable Block Size Motion Estimation in Ultra-High-Definition Video Encoding”, ACM Transactions on Design Automation of Electronic Systems, Volume 24, Issue 2, March 2019.

  21. Di He, Boon Pang Lim, Xuesong Yang, Mark Hasegawa-Johnson, and Deming Chen, “Acoustic landmarks contain more information about the phone string than other frames for automatic speech recognition with deep neural network acoustic model”, The Journal of the Acoustical Society of America, 143, 3207 (2018); doi: 10.1121/1.5039837.

  22. M. Gholipour, Y.Y. Chen, and D. Chen, “Compact Modeling to Device- and Circuit-Level Evaluation of Flexible TMD Field-Effect Transistors,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume: 37, Issue: 4, Page(s): 820 - 831, April 2018.

  23. Chen-Hsuan Lin, Wan Lu, and Deming Chen, “C-Mine: Data Mining of Logic Common Cases for Improved Timing Error Resilience with Energy Efficiency,” ACM Transactions on Design Automation of Electronic Systems, Volume 23 Issue 2, January 2018.

  24. Nam Sung Kim, Deming Chen, Jinjun Xiong, and Wen-mei Hwu, “Heterogeneous Computing Meets Near-Memory Acceleration and High-level Synthesis in the Post-Moore Era”, IEEE Micro, pp. 10-18, Volume: 37, Issue: 4, August 2017.

  25. K. Campbell, W. Zuo, and D. Chen, “New Advances of High-Level Synthesis for Efficient and Reliable Hardware Design”, Integration, the VLSI Journal, Volume 58, Pages 189-214, June 2017. Invited Keynote Paper.

  26. Deming Chen, Jason Cong, Swathi Gurumani, Wen-mei Hwu, Kyle Rupnow, and Zhiru Zhang, “Platform Choices and Design Demands for IoT Platforms: Cost, Power and Performance Tradeoffs”, IET Cyber-Physical Systems: Theory & Applications, pp. 70–77, Vol. 1, Iss. 1, November 2016.

  27. Yun Heo, Anand Ramachandran, Wen-Mei Hwu, Jian Ma, Deming Chen, "BLESS 2: Accurate, memory-efficient, and fast error correction method," Bioinformatics, Volume 32, Issue 15, Pages 2369–2371, 1 August 2016. https://doi.org/10.1093/bioinformatics/btw146.

  28. Y. Chen, T. Nguyen, Y. Chen, S. T. Gurumani, Y. Liang, K. Rupnow, J. Cong, W.M. Hwu, and D. Chen, “FCUDA-HB: Hierarchical and Scalable Bus Architecture Generation on FPGAs with the FCUDA Flow,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 2032-2045, Volume: 35, Issue: 12, 2016.

  29. Y. Chen, S. T. Gurumani, Y. Liang, G. Li, D. Guo, K. Rupnow, and D. Chen, “FCUDA-NoC: A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA Flow”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 2220-2233, Volume: 24, Issue: 6, June 2016.

  30. Y. Liang, M. T. Satria, K. Rupnow, and D. Chen， “An Accurate GPU Performance Model for Effective Control Flow Divergence Optimization”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 1165-1178, Volume: 35, Issue: 7, July 2016.

  31. C. Konigsmark, D. F. Wong, and D. Chen, “PolyPUF: Physically Secure Self-Divergence,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 1053-1066, Volume 35, Issue 7, July 2016.

  32. Y. Wu, J. Zhao, D. Chen, and D. Guo, “Modeling of Gaussian Network-Based Reconfigurable Network-on-Chip Designs”, IEEE Transactions on Computers, pp. 2134-2142, Volume 65, Issue 7, July 2016.

  33. Y.Y. Chen, A. Sangai, A. Rogachev, M. Gholipour, G. Iannaccone, G. Fiori, and D. Chen, “A SPICE-Compatible Model of MOS-Type Graphene Nano-ribbon Field-Effect Transistors enabling Gate- and Circuit-level Delay and Power Analysis under Process Variation,” IEEE Transactions on Nanotechnology, Volume 14, Issue 6, pp. 1068-1082, November 2015.

  34. X. Xie, Y. Liang, G. Sun, and D. Chen, “An Efficient Compiler Framework for Cache Bypassing on GPUs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 34, No. 10, pp. 1677-1690, October 2015.

  35. M. Gholipour, Y.Y. Chen, A. Sangai, N. Masoumi, and D. Chen, “Analytical SPICE-Compatible Model of Schottky-Barrier-Type GNRFETs With Performance Analysis”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, March 2015.

  36. N. Liu, H. Li, H. Dai, D. Guo, and D. Chen, “Robust Blind Image Watermarking Based on Chaotic Mixtures”, Nonlinear Dynamics, Vol 80, Issue 3, pp 1329-1355, May 2015.

  37. H. Zheng, S. T. Gurumani, L. Yang, D. Chen, and K. Rupnow, "High-level Synthesis with Behavioral-level Multi-cycle Path Analysis," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol 33, No. 12, pp 1832-1845, December 2014.

  38. M. Gholipour, N. Masoumi, Y-Y. Chen, D. Chen, and M. Pourfath, "Asymmetric Gate Schottky-Barrier Graphene Nano-Ribbon FETs for Low Power Design," IEEE Transactions on Electron Devices, Vol. 61, No. 12, December 2014.

  39. Z. Zhang, D. Chen, S. Dai, and K. Campbell, "High-Level Synthesis for Low-Power Design," IPSJ Transactions on System LSI Design Methodology, Vol. 8 (2015) pp. 12-25, February 2015. (Invited)

  40. H. Luo, S. Wei, D. Chen, and D. Guo, "Hybrid Circuit-Switched Network for On-Chip Communication in Large-Scale Chip-Multiprocessors," Journal of Parallel and Distributed Computing, Vol 74, Issue 9, pp. 2818-2830, September 2014.

  41. Y. Liang, H. P. Huynh, K. Rupnow, S. M. Goh, and D. Chen, "Efficient GPU Spatial-Temporal Multitasking," IEEE Transactions on Parallel and Distributed Systems, VOl. PP, Issue 99, March 2014.

  42. Y. Heo, X-L. Wu, D. Chen, J. Ma, and W-M Hwu, "BLESS: Bloom-filter-based Error Correction Solution for High throughput Sequencing Reads," Bioinformatics, 2014.

  43. T. Yan, Q. Ma, S. Chilstedt, M. D.F. Wong, and D. Chen, "A Routing Algorithm for Graphene Nanoribbon Circuit," ACM Transactions on Design Automation of Electronic Systems - Special Section on Networks on Chip: Architecture, Tools, and Methodologies, Vol. 18, Issue 4, October 2013.

  44. A. Papakonstantinou, K. Gururaj, J. Stratton, D. Chen, J. Cong, and W-M. Hwu, "Efficient Compilation of CUDA Kernels for High-Performance Computing on FPGAs," ACM Transactions on Embedded Computing Systems, Special Issue on Application-Specific Processors, Vol. 13, Issue 2, September 2013.

  45. X-L. Wu, Heo Y, I. El Hajj, W-M. Hwu, D. Chen, and J. Ma. "TIGER: Tiled Iterative Genome Assembler," BMC Bioinformatics, 2012, 13(Suppl 19):S18, 19 December 2012.

  46. L. Wan, C. Dong and D. Chen, "A Coarse-Grained Reconfigurable Architecture with Compilation for High Performance", International Journal of Reconfigurable Computing, Special Issue on High Performance Reconfigurable Computing, Volume 2012 (2012), Article ID 163542, 17 pages, 2012.

  47. L. Wan and D. Chen, "Analysis of Digital Circuit Dynamic Behavior with Timed Ternary Decision Diagrams for Better-Than-Worst-Case Design," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 31, No. 5, pp. 662-675, May 2012.

  48. Y. Liang, K. Rupnow, Y. Li, D. Min, M. Do, and D. Chen, "High Level Synthesis: Productivity, Performance and Software Constraints", Journal of Electrical and Computer Engineering, Special Issue on ESL Design Methodology, Volume 2012 (2012), Article ID 649057, 14 pages, 2012.

  49. D. Chen, J. Cong, C. Dong, L. He, F. Li, and C. Peng, "Technology Mapping and Clustering for FPGA Architectures with Dual Supply Voltages," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 29, No. 11, pp. 1709-1722, Nov. 2010.

  50. G. Lucas, C. Dong, and D. Chen, "Variation-Aware Placement with Multi-cycle Statistical Timing Analysis for FPGAs," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 29, No. 11, pp. 1818-1822, Nov. 2010.

  51. S. Akram, A. Papakonstantinou, R. Kumar, and D. Chen, "Workload Adaptive Shared Memory Multicore Processors with Reconfigurable Interconnects," Journal of Reconfigurable Computing, Vol. 2010, Article ID 205852, 22 pages, 2010.

  52. Q. Dinh, D. Chen, and D. F. Wong, "A Routing Approach to Reduce Glitches in Low Power FPGAs", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 29, No. 2, pp. 235-240, February 2010.

  53. D. Chen, J. Cong, Y. Fan, and L. Wan, "LOPASS: A Low-Power Architectural Synthesis System for FPGAs with Interconnect Estimation and Optimization", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 18, No. 4, pp. 564-577, April 2010.

  54. D. Chen and S. Cromar, "An Optimal Resource Binding Algorithm with Inter-Transition Switching Activities for Low Power", Journal of Low Power Electronics, Vol. 5, No. 4, pp. 454-463, December 2009.

  55. S. Chilstedt, C. Dong, and D. Chen, "Design and Evaluation of a Carbon Nanotube-Based Programmable Architecture", International Journal of Parallel Programming (IJPP), Special Issue on Nano/Bio-Inspired Applications, Architectures and Software, Vol. 37, Issue 4, pp. 389-416, August 2009.

  56. H. Li, D. H. Kwon, D. Chen, and Y. Chiu, "A Fast Digital Predistortion Algorithm for Radio-Frequency Power Amplifier Linearization with Loop Delay Compensation," IEEE Journal of Selected Topics in Signal Processing, Special Issue on: DSP Techniques for RF/Analog Circuit Impairments, Vol. 3, No. 3, pp.374-383, June 2009.

  57. L. Cheng, D. Chen, and D.F. Wong, "DDBDD: Delay-Driven BDD Synthesis for FPGAs", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27, No. 7, pp.1203-1213, July 2008.

  58. L. Cheng, D. Chen, and D.F. Wong, "A Fast Simultaneous Input Vector Generation and Gate Replacement Algorithm for Leakage Power Reduction," ACM Transactions on Design Automation of Electronic Systems, Vol. 13, No. 2, Article 34, pp. 1-15, April 2008.

  59. C. Dong, D. Chen, S. Haruehanroengra, and W. Wang, "3-D nFPGA: A Reconfigurable Architecture for 3-D CMOS/Nanomaterial Hybrid Digital Circuits," IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, Vol. 54, Issue 11, pp. 2489-2501, November 2007.

  60. D. Chen, J. Cong, and J. Xu, "Optimal Simultaneous Module and Multi-Voltage Assignment for Low-Power," ACM Transactions on Design Automation of Electronic Systems, vol. 11, Issue 2, pp. 362-386, April 2006.

  61. F. Li, Y. Lin, L. He, D. Chen, and J. Cong, "Power Modeling and Characteristics of Field Programmable Gate Arrays," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, Issue 11, pp. 1712-1724, November 2005. (One of the most-downloaded papers from TCAD ranked by CEDA)

  62. D. Chen, J. Cong, M. Ercegovac, and Z. Huang, "Performance-Driven Mapping for CPLD Architectures," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 10, pp. 1424-1431, October 2003.

CONFERENCE PAPERS


  1. Hanchen Ye, Hyegang Jun, and Deming Chen, “HIDA: A Hierarchical Dataflow Compiler for High-Level Synthesis”, Proceedings of ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), April 2024.

  2. Hanchen Ye, David Pan, Chris Leary, Deming Chen, and Xiaoqing Xu, “Subgraph Extraction-based Feedback-guided Iterative Scheduling for HLS”, Proceedings of the Conference on Design, Automation & Test in Europe (DATE), March 2024.

  3. Lily Jiaxin Wan, Yingbing Huang, Yuhong Li, Hanchen Ye, Jinghua Wang, Xiaofan Zhang, and Deming Chen, “Invited: Software/Hardware Co-design for LLM and Its Application for Design Verification,” Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, January 2024. (Invited)

  4. Zehua Yuan, Junhao Pan, Xiaofan Zhang, and Deming Chen, “HomeSGN: A Smarter Home with Novel Rule Mining Enabled by a Scorer-Generator GAN”, Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, January 2024.

  5. Yizhen Lu, Curtis Yu, and Deming Chen, “SSDe: FPGA-based SSD Express Emulation Framework,” Proceedings of IEEE/ACM International Conference on Computer-Aided Design, October 2023.

  6. Benjamin Reidys, Yuqi Xue, Yiqi Liu, Daixuan Li, Bharat Sukhwani, Wen-mei Hwu, Deming Chen, Sameh Asaad, and Jian Huang, “RackBlox: A Software-Defined Rack-Scale Storage System with Network-Storage Co-Design,” Proceedings of the Symposium on Operating Systems Principles, October 2023.

  7. Yuhong Li, Jiajie Li, Cong Hao, Pan Li, Jinjun Xiong, and Deming Chen, “Extensible and Efficient Proxy for NAS,” Proceedings of the International Conference on Computer Vision (ICCV), October 2023.

  8. Luyang Yu, Yizhen Lu, Meghna Mandava, Edward Richter, Vikram Sharma Mailthody, Seung Won Min, Wen-Mei Hwu, and Deming Chen, “FSSD: FPGA-based Emulator for SSDs,” Proceedings of the International Conference on Field-Programmable Logic and Applications, September 2023.

  9. Deming Chen, “Lightning Talk: The Next Wave of High-level Synthesis,” Proceedings of ACM/IEEE Design Automation Conference, July 2023. (Invited)

  10. Wei Ren, William Kozlowski, Sandhya Koteshwara, Mengmei Ye, Hubertus Franke, and Deming Chen, “AccShield: a New Trusted Execution Environment with Machine-Learning Accelerators,” Proceedings of ACM/IEEE Design Automation Conference, July 2023.

  11. Meghna Mandava, Paul Reckamp, and Deming Chen, “Nimblock: Scheduling for Fine-grained FPGA Sharing through Virtualization,” Proceedings of International Symposium on Computer Architecture, June 2023.

  12. Yuhong Li, Tianle Cai, Yi Zhang, Deming Chen, and Debadeepta Dey, “What Makes Convolutional Models Great on Long Sequence Modeling?” Proceedings of International Conference on Learning Representations, May 2023.

  13. Hanchen Ye, Hyegang Jun, Jin Yang, and Deming Chen “High-level Synthesis for Domain Specific Computing,” Proceedings of International Symposium on Physical Design, March 2023. (Invited)

  14. Jinming Zhuang, Jason Lau, Hanchen Ye, Zhuoping Yang, Yubo Du, Jack Lo, Kristof Denolf, Stephen Neuendorffer, Alex Jones, Jingtong Hu, Deming Chen, Jason Cong, and Peipei Zhou, “CHARM: Composing Heterogeneous Accelerators for Matrix Multiply on Versal ACAP Architecture,” Proceedings of ACM/SIGDA International Symposium on Field Programmable Gate Arrays, February 2023.

  15. Junhao Pan, Zehua Yuan, Xiaofan Zhang, and Deming Chen, “YouHome System and Dataset: Making Your Home Know You Better”, Proceedings of IEEE International Symposium on Smart Electronic Systems, December 2022.

  16. Vibhakar Vemulapati and Deming Chen, “FSLAM: an Efficient and Accurate SLAM Accelerator on SoC FPGAs”, Proceedings of IEEE International Conference on Field Programmable Technology, December 2022.

  17. Hongpeng Guo, Haotian Gu, Zhe Yang, Xiaoyang Wang, Eun Kung Lee, Nandhini Chandramoorthy, Tamar Eilam, Deming Chen, and Klara Nahrstedt, “BoFL: Bayesian Optimized Local Training Pace Control for Energy Efficient Federated Learning,” Proceedings of ACM/IFIP International Middleware Conference (Middleware’22), November 2022.

  18. Edward Richter and Deming Chen, “Qilin: Enabling Performance Analysis and Optimization of Shared-Virtual Memory Systems with FPGA Accelerators,” Proceedings of IEEE/ACM International Conference on Computer-Aided Design, November 2022.

  19. Hanchen Ye, Gregory Jun, Hyunmin Jeong, Stephen Neuendorffer, and Deming Chen, “Invited: ScaleHLS, a Scalable High-level Synthesis Framework with Multi-level Transformations and Optimizations,” Proceedings of IEEE/ACM Design Automation Conference, July 2022. (Invited)

  20. Hanchen Ye, Cong Hao, Jianyi Cheng, Hyunmin Jeong, Jack Huang, Stephen Neuendorffer, and Deming Chen, “ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representation,” Proceedings of IEEE International Symposium on High-Performance Computer Architecture (HPCA), April 2022.

  21. Prakhar Ganesh, Yao Chen, Yin Yang, Deming Chen, and Marianne Winslett, “YOLO-ReT: Towards High Accuracy Real-time Object Detection on Edge GPUs”, Proceedings of Winter Conference on Applications of Computer Vision, January 2022.

  22. Xinheng Liu, Yao Chen, Prakhar Ganesh, Junhao Pan, Jinjun Xiong, and Deming Chen, “HiKonv: High Throughput Quantized Convolution with Novel Bit-wise Management and Computation”, Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, January 2022.

  23. Wei Ren, Junhao Pan, and Deming Chen, “AccGuard: Secure and Trusted Computation on Remote FPGA Accelerators”, Proceedings of IEEE International Symposium on Smart Electronic Systems, December 2021.

  24. Xinyu Chen, Hongshi Tan, Yao Chen, Bingsheng He, Weng-Fai Wong, and Deming Chen, “Skew-oblivious Data Routing for Data Intensive Applications on FPGAs with HLS," Proceedings of IEEE/ACM Design Automation Conference, December 2021.

  25. Xiaofan Zhang, Dawei Wang, Pierce Chuang, Shugao Ma, Deming Chen, and Yuecheng Li, "F-CAD: A Framework to Explore Hardware Accelerators for Codec Avatar Decoding," Proceedings of IEEE/ACM Design Automation Conference, December 2021.

  26. Yuhong Li, Cong Hao, Pan Li, Jinjun Xiong, and Deming Chen, “Generic Neural Architecture Search via Regression.” Proceedings of Conference on Neural Information Processing Systems (NeurIPS), December 2021. (Spotlight paper, < 3% of 9122 full paper submissions)

  27. Sitao Huang, Kun Wu, Sai Rahul Chalamalasetti, Izzat El Hajj, Cong Xu, Paolo Faraboschi, and Deming Chen, “A Python-based High-Level Programming Flow for CPU-FPGA Heterogeneous Systems,” Proceedings of the Workshop for Programming Environments for Heterogeneous Computing (co-located with SC21), November 2021.

  28. Mang Yu, Sitao Huang, and Deming Chen, “Chimera: A Hybrid Machine Learning-Driven Multi-Objective Design Space Exploration Tool for FPGA High-Level Synthesis”, Proceedings of International Conference on Intelligent Data Engineering and Automated Learning, November 2021. (Best Paper Award)

  29. S. Chattopadhyay, F. Lonsing, L. Piccolboni, D. Soni, P. Wei, X. Zhang, Y. Zhou, L. Carloni, D. Chen, J. Cong, R. Karri, Z. Zhang, C. Trippel, C. Barrett and S. Mitra, “Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition,” Proceedings of Formal Methods in Computer-Aided Design, October 2021.

  30. Enliang Li, Subho S. Banerjee, Sitao Huang, Ravishankar K. Iyer, and Deming Chen, “Improved GPU Implementations of the Pair-HMM Forward Algorithm for DNA Sequence Alignment”, Proceedings of IEEE International Conference on Computer Design, October 2021.

  31. Seung Won Min, Kun Wu, Sitao Huang, Mert Hidayetoğlu, Jinjun Xiong, Eiman Ebrahimi, Deming Chen, and Wen-mei Hwu, “Large Graph Convolutional Network Training with GPU-Oriented Data Communication Architecture”, Proceedings of the International Conference on Very Large Data Bases, August 2021.

  32. Xinheng Liu, Yao Chen, Cong Hao, Ashutosh Dhar, and Deming Chen, “WinoCNN: Kernel Sharing Winograd Systolic Array for Efficient Convolutional Neural Network Acceleration on FPGAs”, Proceedings of IEEE International Conference on Application-specific Systems, Architectures and Processors, July 2021.

  33. Hyunmin Jeong and Deming Chen, “TwinDNN: A Tale of Two Deep Neural Networks”, Proceedings of IEEE International Conference on Application-specific Systems, Architectures and Processors, July 2021.

  34. Cong Hao and Deming Chen, “Software/Hardware Co-design for Multimodal Multi-task Learning in Autonomous Systems”, Proceedings of IEEE International Conference on Artificial Intelligence Circuits and Systems, June 2021. (Invited)

  35. Ashutosh Dhar, Paul Reckamp, Jinjun Xiong, Wen-mei Hwu, and Deming Chen, “Graviton: A Reconfigurable Memory-Compute Fabric for Data Intensive Applications”, Proceedings of International Symposium on Applied Reconfigurable Computing, June 2021.

  36. Xinyu Chen, Hongshi Tan, Yao Chen, Bingsheng He, Weng-Fai Wong, and Deming Chen, “ThunderGP: HLS-based Graph Processing Framework on FPGAs”, Proceedings of ACM/SIGDA International Symposium on Field Programmable Gate Arrays, February 2021.

  37. Yichi Zhang, Junhao Pan, Xinheng Liu, Hongzheng Chen, Deming Chen and Zhiru Zhang, “FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations,” Proceedings of ACM/SIGDA International Symposium on Field Programmable Gate Arrays, February 2021. (Best Paper Candidate)

  38. Junhao Pan and Deming Chen, “Accelerate Non-unit Stride Convolutions with Winograd Algorithms”, Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, January 2021.

  39. Sitao Huang, Aayush Ankit, Plinio Silveira, Rodrigo Antunes, Sai Rahul Chalamalasetti, Izzat El Hajj, Dong-Eun Kim, Glaucimar Aguiar, Pedro Bruel, Sergey Serebryakov, Cong Xu, Can Li, Paolo Faraboschi, John Paul Strachan, Deming Chen, Kaushik Roy, Wen-mei Hwu, and Dejan Milojicic, "Mixed Precision Quantization for ReRAM-based DNN Inference Accelerators," Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, January 2021. (Best Paper Candidate)

  40. Xiaofan Zhang, Hanchen Ye, Junsong Wang, Yonghua Lin, JinJun Xiong, Wen-mei Hwu, and Deming Chen, “DNNExplorer: A Framework for Modeling and Exploring a Novel Paradigm of FPGA-based DNN Accelerator,” Proceedings of IEEE/ACM International Conference on Computer-Aided Design, November 2020.

  41. Ashutosh Dhar, Xiaohao Wang, Hubertus Franke, Jinjun Xiong, Jian Huang, Wen-mei Hwu, Nam Sung Kim, and Deming Chen, “FReaC Cache: Folded Logic Reconfigurable Computing in the Last Level Cache”, Proceedings of 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), October 2020.

  42. Cong Hao, Yao Chen, Xiaofan Zhang, Yuhong Li, Jinjun Xiong, Wen-mei Hwu, and Deming Chen, “Effective Algorithm-Accelerator Co-design for AI Solutions on Edge Devices”, Proceedings of ACM Great Lakes Symposium on VLSI, September 2020. (Invited)

  43. Sitao Huang, Deming Chen, and Wen-mei Hwu, “PyLog: Algorithm-Centric FPGA Programming and Synthesis,” Proceedings of SRC TECHCON, September 2020.

  44. Junhao Pan and Deming Chen, “A Method for Faster Non-unit Stride Convolution in Deep Neural Networks,” Proceedings of SRC TECHCON, September 2020.

  45. Xinheng Liu, Cong Hao, Yao Chen, Ashutosh Dhar, and Deming Chen, "Wino-SA: Efficient Systolic Architecture for Winograd Convolution," Proceedings of SRC TECHCON, September 2020.

  46. Cong Hao and Deming Chen, "Efficient Differentiable DNN Architecture and Implementation Co-search for Heterogeneous AI Devices," Proceedings of SRC TECHCON, September 2020.

  47. Eshan Singh, Florian Lonsing, Saranyu Chattopadhyay, Max Strange, Peng Wei, Xiaofan Zhang, Yuan Zhou, Jason Cong, Deming Chen, Zhiru Zhang, Priyanka Raina, Clark Barrett, Subhasish Mitra, “A-QED Verification of Hardware Accelerators,” Proceedings of IEEE/ACM Design Automation Conference, July 2020.

  48. Yuhong Li, Cong Hao, Xiaofan Zhang, Xinheng Liu, Yao Chen, Jinjun Xiong, Wen-mei Hwu, and Deming Chen, “EDD: Efficient Differentiable DNN Architecture and Implementation Co-search for Embedded AI Solutions,” Proceedings of IEEE/ACM Design Automation Conference, July 2020.

  49. Hanchen Ye, Xiaofan Zhang, Zhize Huang, Gengsheng Chen, and Deming Chen, “HybridDNN: A Framework for High-Performance Hybrid DNN Accelerator Design and Implementation,” Proceedings of IEEE/ACM Design Automation Conference, July 2020.

  50. Yao Chen, Xin Long, Jiong He, Yuhang Chen, Hongshi Tan, Zhenxiang Zhang, Marianne Winslett, and Deming Chen, “HaoCL: Harnessing Large-scale Heterogeneous Processors Made Easy,” Proceedings of IEEE International Conference on Distributed Computing Systems, July 2020.

  51. Xiaofan Zhang, Haoming Lu, Cong Hao, Jiachen Li, Bowen Cheng, Yuhong Li, Kyle Rupnow, Jinjun Xiong, Thomas Huang, Honghui Shi, Wen-Mei Hwu, and Deming Chen, “SkyNet: a Hardware-Efficient Method for Object Detection and Tracking on Embedded Systems,” Proceedings of Machine Learning and Systems (MLSys 2020), March 2020.

  52. Pengfei Xu, Xiaofan Zhang, Cong Hao, Yang Zhao, Yongan Zhang, Yue Wang, Chaojian Li, Zetong Guan, Deming Chen, and Yingyan Lin, “AutoDNNchip: An Automated DNN Chip Predictor and Builder for Both FPGAs and ASICs”, Proceedings of ACM/SIGDA International Symposium on Field Programmable Gate Arrays, February 2020.

  53. Xinyu Chen, Yao Chen, Ronak Bajaj, Jiong He, Bingsheng He, Weng-Fai Wong, and Deming Chen, “Is FPGA Useful for Hash Joins?”, Proceedings of Conference on Innovative Data Systems Research (CIDR), January 2020.

  54. Ashutosh Dhar, Mang Yu, Wei Zuo, Xiaohao Wang, Nam Sung Kim, and Deming Chen, “Leveraging Dynamic Partial Reconfiguration with Scalable ILP Based Task Scheduling,” Proceedings of IEEE International Conference on VLSI Design, January 2020. (Best Paper Award)

  55. Dae Hee Kim, Rakesh Nagi, and Deming Chen, “Thanos: High-Performance CPU-GPU Based Graph Partitioning Using Cross-Decomposition,” Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, January 2020.

  56. Weijie You, Deming Chen, and Chang Wu, “A Flexible DNN Accelerator Design with Layer Pipeline for FPGAs,” Proceedings of International Conference on Information Science and Control Engineering, December 2019.

  57. Cong Hao, Yao Chen, Xinheng Liu, Atif Sarwari, Daryl Sew, Ashutosh Dhar, Bryan Wu, Dongdong Fu, Jinjun Xiong, Wen-mei Hwu, Junli Gu, and Deming Chen, “NAIS: Neural Architecture and Implementation Search and its Applications in Autonomous Driving,” Proceedings of IEEE/ACM International Conference on Computer-Aided Design, November 2019. (Invited)

  58. Cong Hao, Atif Sarwari, Zhijie Jin, Husam Abu-Haimed, Daryl Sew, Yuhong Li, Xinheng Liu, Bryan Wu, Dongdong Fu, Junli Gu, and Deming Chen, “A Hybrid GPU + FPGA System Design for Autonomous Driving Cars,” Proceedings of IEEE International Workshop on Signal Processing Systems, October 2019. (Invited)

  59. Sitao Huang, Deming Chen, and Wen-Mei Hwu, "Accelerating Sparse Deep Neural Network on FPGA,” Proceedings of IEEE High Performance Extreme Computing Conference (HPEC), September 2019. (Honorable Mention)

  60. Xinyu Chen, Ronak Bajaj, Yao Chen, Jiong He, Bingsheng He, Weng-Fai Wong and Deming Chen, “On-The-Fly Parallel Data Shuffling for Graph Processing on OpenCL based FPGA”, Proceedings of International Conference on Field-Programmable Logic and Applications, September, 2019.

  61. Seung Won Min, Sitao Huang, Mohamed Aly, Jinjun Xiong, Deming Chen and Wen-Mei Hwu, “Analysis and Optimization of I/O Cache Coherency Strategies for SoC-FPGA Device”, Proceedings of International Conference on Field-Programmable Logic and Applications, September, 2019.

  62. Cheng Gong, Ye Lu, Cong Hao, Xiaofan Zhang, Tao Li, Deming Chen, and Yao Chen, “𝜇L2Q: An Ultra-Low Loss Quantization Method for DNN Compression,” Proceedings of International Joint Conference on Neural Networks (IJCNN), July 2019.

  63. Ashutosh Dhar, Sitao Huang, Jinjun Xiong, Damir Jamsek, Bruno Mesnet, Jian Huang, Nam Sung Kim, Wen-mei Hwu, and Deming Chen, “Near-Memory and In-Storage FPGA Acceleration for Emerging Cognitive Computing Workloads,” Proceedings of IEEE Computer Society Annual Symposium on VLSI, July 2019. (Invited)

  64. Yao Chen, Kai Zhang, Cheng Gong, Cong Hao, Xiaofan Zhang, Tao Li, and Deming Chen, “T-DLA: An Open-source Deep Learning Accelerator for Ternarized DNN Models on Embedded FPGA,” Proceedings of IEEE Computer Society Annual Symposium on VLSI, July 2019.

  65. Jong Bin Lim and Deming Chen, “Automated Communication and Floorplan-Aware Hardware/Software Co-Design for SoC,” Proceedings of IEEE Computer Society Annual Symposium on VLSI, July 2019.

  66. Youjie Li, Iou-Jen Liu, Yifan Yuan, Deming Chen, Alexander Schwing, and Jian Huang, “Accelerating Distributed Reinforcement Learning with In-Switch Computing,” Proceedings of International Symposium on Computer Architecture, June 2019.

  67. Eric Cheng, Daniel-Mueller-Gritschneder, Jacob Abraham, Pradip Bose, Alper Buyuktosunoglu, Deming Chen, Hyungmin Cho, Yanjing Li, Uzair Sharif, Kevin Skadron, Mircea Stan, Ulf Schlichtmann, and Subhasish Mitra, “Cross-Layer Resilience: Challenges, Insights, and the Road Ahead,” Proceedings of IEEE/ACM Design Automation Conference, June 2019. (Invited)

  68. C. Hao, X. Zhang, Y. Li, S. Huang, J. Xiong, K. Rupnow, W.M. Hwu, and D. Chen, “FPGA/DNN Co-Design: An Efficient Design Methodology for IoT Intelligence on the Edge”, Proceedings of IEEE/ACM Design Automation Conference, June 2019.

  69. Yi Liang, Di He, and Deming Chen, “Poisoning Attack on Load Forecasting,” Proceedings of IEEE PES Innovative Smart Grid Technologies Asia, May 2019.

  70. Di He, Xuesong Yang, Boon Pang Lim, Yi Liang, Mark Hasegawa-Johnson, and Deming Chen, “When CTC Training Meets Acoustic Landmarks,” Proceedings of IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), May 2019.

  71. Anand Ramachandran, Eric Klee, Steven Lumetta, and Deming Chen, “A Recurrent Markov State-space Generative Model for Sequences,” Proceedings of International Conference on Artificial Intelligence and Statistics, Apr. 2019.

  72. Sitao Huang, Li-Wen Chang, Izzat El Hajj, Simon Garcia de Gonzalo, Juan Gómez Luna, Sai Rahul Chalamalasetti, Mohamed El-Hadedy, Dejan Milojicic, Onur Mutlu, Deming Chen, and Wen-mei Hwu, “Collaborative Computing on Heterogeneous CPU-FPGA Architectures Using OpenCL,” Proceedings of ACM/SPEC International Conference on Performance Engineering, Apr. 2019.

  73. Yao Chen, Jiong He, Xiaofan Zhang, Cong Hao, and Deming Chen, “Cloud-DNN: An Open Framework for Mapping DNN Models to Cloud FPGAs”, Proceedings of ACM/SIGDA International Symposium on Field Programmable Gate Arrays, February 2019.

  74. Qin Li, Xiaofan Zhang, Jinjun Xiong, Wen-mei Hwu, and Deming Chen, “Implementing Neural Machine Translation with Bi-Directional GRU and Attention Mechanism on FPGAs Using HLS,” Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, January 2019.

  75. Xiaofan Zhang, Junsong Wang, Chao Zhu, Yonghua Lin, Jinjun Xiong, Wen-mei Hwu, and Deming Chen, “DNNBuilder: an Automated Tool for Building High-Performance DNN Hardware Accelerators for FPGAs”, Proceedings of IEEE/ACM International Conference on Computer-Aided Design, November 2018. (Best Paper Award)

  76. Cong Hao and Deming Chen, “Deep Neural Network Model and FPGA Accelerator Co-design: Opportunities and Challenges”, Proceedings of IEEE International Conference on Solid-State and Integrated Circuit Technology, October 2018. (Invited)

  77. Mohammad Alian, Seung Won Min, Hadi Asgharimoghaddam, Ashutosh Dhar, Dong Kai Wang, Thomas Roewer, Adam McPadden, Oliver OHalloran, Deming Chen, Jinjun Xiong, Daehoon Kim, Wen-mei Hwu, and Nam Sung Kim, “Application-transparent near-memory processing architecture with memory channel network,” Proceedings of IEEE/ACM International Symposium on Microarchitecture (MICRO), October, 2018. (Best Paper Award Candidate)

  78. Sitao Huang, Mohamed El-Hadedy, Cong Hao, Qin Li, Vikram Sharma Mailthody, Ketan Date, Jinjun Xiong, Deming Chen, Rakesh Nagi and Wen-Mei Hwu, “Triangle Counting and Truss Decomposition using FPGA,” Proceedings of IEEE High Performance Extreme Computing Conference (HPEC), September 2018. (Student Innovation Award)

  79. Di He, Boon Pang Lim, Xuesong Yang, Mark Hasegawa-Johnson, and Deming Chen, “Improved ASR for Under-Resourced Languages Through Multi-Task Learning with Acoustic Landmarks”, Proceedings of Annual Conference of the International Speech Communication Association, September 2018.

  80. Junsong Wang, Qiuwen Lou, Xiaofan Zhang, Chao Zhu, Yonghua Lin and Deming Chen, “A Design Flow of Accelerating Hybrid Extremely Low Bit-width Neural Network in Embedded FPGA”, Proceedings of International Conference on Field-Programmable Logic and Applications, August 2018.

  81. Huiren Li, Anand Ramachandran, and Deming Chen, “GPU Acceleration of Advanced k-mer Counting for Computational Genomics”, Proceedings of IEEE International Conference on Application-specific Systems, Architectures and Processors, July 2018.

  82. Xinheng Liu, Dae Hee Kim, Chang Wu and Deming Chen, “Resource and Data Optimization for Hardware Implementation of Deep Neural Networks Targeting FPGA-based Edge Devices”, Proceedings of IEEE/ACM International Workshop on System-Level Interconnect Prediction, June 2018. (Best Paper Award)

  83. Y. Li, X. Zhang and D. Chen, “CSRNet: Dilated Convolutional Neural Networks for Understanding the Highly Congested Scenes,” Proceedings of Conference on Computer Vision and Pattern Recognition, June 2018.

  84. Chuanhao Zhuge, Xinheng Liu, Xiaofan Zhang, Sudeep Gummadi, Jinjun Xiong, and Deming Chen, “Face Recognition with Hybrid Efficient Convolution Algorithms on FPGAs,” Proceedings of ACM/IEEE Great Lakes Symposium on VLSI, May 2018.

  85. Anand Ramachandran, Huiren Li, Eric Klee, Steven Lumetta, and Deming Chen, “Deep Learning for Better Variant Calling for Cancer Diagnosis and Treatment”, Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, January 2018. (Invited)

  86. Keith Campbell, Chen-Hsuan Lin, and Deming Chen, “Low-Cost Hardware Architectures for Mersenne Modulo Functional Units”, Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, January 2018.

  87. Eric Cheng, Jacob Abraham, Pradip Bose, Alper Buyuktosunoglu, Keith Campbell, Deming Chen, Cheng-Yong Cher, Hyungmin Cho, Binh Le, Klas Lilja, Shahrzad Mirkhani, Kevin Skadron, Mircea Stan, Lukasz Szafaryn8, Christos Vezyrtzis, and Subhasish Mitra, “Cross-Layer Resilience in Low-Voltage Digital Systems: Key Insights,” Proceedings of IEEE International Conference on Computer Design, November 2017. (Invited)

  88. Xiaofan Zhang, Anand Ramachandran, Chuanhao Zhuge, Di He, Wei Zuo, Zuofu Cheng, Kyle Rupnow, and Deming Chen, “Machine Learning on FPGAs to Face the IoT Revolution,” Proceedings of IEEE/ACM International Conference on Computer-Aided Design, November 2017. (Invited)

  89. Wen-mei Hwu, Izzat El Hajj, Simon Garcia de Gonzalo, Carl Pearson, Nam Sung Kim, Deming Chen, Jinjun Xiong, and Zehra Sura, “Rebooting the Data Access Hierarchy of Computing Systems,” Proceedings of IEEE International Conference on Rebooting Computing, November 2017. (Invited)

  90. Keith Campbell, Eric Cheng, Subhasish Mitra, and Deming Chen, “Cost-Effective Cross-Layer Resilience for Hardware Accelerators,” Proceedings of TECHCON, September 2017.

  91. Sitao Huang, Simon Garcia De Gonzalo, Li-Wen Chang, Izzat El Hajj, Juan Gómez-Luna, Sai Rahul Chalamalasetti, Mohamed El Hadedy, Dejan Milojicic, Deming Chen, and Wen-mei Hwu, “Collaborative Computing on Heterogeneous CPU-FPGA Systems”, Proceedings of TECHCON, September 2017.

  92. Xiaofan Zhang, Xinheng Liu, Anand Ramachandran, Chuanhao Zhuge, Shibin Tang, Peng ouyang, Zuofu Cheng, Kyle Rupnow and Deming Chen, “High-Performance Video Content Recognition with Long-term Recurrent Convolutional Network for FPGA”, Proceedings of International Conference on Field-Programmable Logic and Applications, September 2017.

  93. Di He, Zuofu Cheng, Mark Hasegawa-Johnson, and Deming Chen, “Using Approximated Auditory Roughness as a Pre-filtering Feature for Human Screaming and Affective Speech AED,” Proceedings of Interspeech, August 2017.

  94. Sven Tenzing Choden Konigsmark, Deming Chen, and Martin Wong, “High-Level Synthesis for Side-Channel Defense,” Proceedings of IEEE International Conference on Application-specific Systems, Architectures and Processors, July 2017.

  95. W. Zuo, T. Kim, A. Ayupov, C.W Lin, S. Shiraishi, L.N. Pouchet, and D. Chen, “Accurate High-level Modeling and Automated Hardware/Software Co-design for Effective SoC Design Space Exploration,” Proceedings of IEEE/ACM Design Automation Conference, June 2017.

  96. A. Dhar and D. Chen, “Efficient GPGPU Computing with Cross-Core Resource Sharing and Core Reconfiguration,” Proceedings of IEEE International Symposium on Field-Programmable Custom Computing Machines, May 2017.

  97. L.W. Chang, J. Gómez-Luna, I. Hajj, S. Huang, D. Chen, and W.M. Hwu, “Collaborative Computing for Heterogeneous Integrated Systems,” Proceedings of ACM/SPEC International Conference on Performance Engineering, April 2017.

  98. S. Huang, G. J. Manikandan, A. Ramachandran, K. Rupnow, W.M. Hwu, and D. Chen, “Hardware Acceleration of the Pair-HMM Algorithm for DNA Variant Calling”, Proceedings of ACM/SIGDA International Symposium on Field Programmable Gate Arrays, February 2017.

  99. W. Kemmerer, W. Zuo, and D. Chen, "Parallel Code-Specific CPU Simulation with Dynamic Phase Convergence Modeling for HW/SW Co-Design", Proceedings of IEEE/ACM International Conference on Computer-Aided Design, November 2016.

  100. T. Nguyen, Y. Chen, K. Rupnow, S. Gurumani, and D. Chen, "SoC, NoC and Hierarchical Bus Implementations of Applications on FPGAs Using the FCUDA Flow", Proceedings of IEEE Computer Society Annual Symposium on VLSI, July 2016. (Invited)

  101. K. Campbell, L. He, L. Yang, S. Gurumani, K. Rupnow, and D. Chen, "Debugging and Verifying SoC Designs through Effective Cross-Layer Hardware-Software Co-simulation," Proceedings of IEEE/ACM Design Automation Conference, June 2016.

  102. S. T. C. Konigsmark, D. F. Wong, and D. Chen, "Information Dispersion for Trojan Defense through High-Level Synthesis," Proceedings of IEEE/ACM Design Automation Conference, June 2016.

  103. L. Yang, S. Gurumani, D. Chen, and K. Rupnow, "AutoSLIDE: Automatic Source-Level Instrumentation and Debugging for HLS," Proceedings of IEEE International Symposium on Field-Programmable Custom Computing Machines, May 2016.

  104. M. T. Satria, W. Zheng, S. Gurumani, K. P. Tee, A. Koh, P. Yu, K. Rupnow, and D. Chen，“Real-Time System-Level Implementation of a Telepresence Robot Using an Embedded GPU Platform,” Proceedings of IEEE/ACM Design, Automation & Test in Europe, March 2016.

  105. X. Liu, Y. Chen, T. Nguyen, S. Gurumani, K. Rupnow, and D. Chen, “High Level Synthesis of Complex Applications: An H.264 Video Decoder”, Proceedings of ACM/SIGDA International Symposium on Field Programmable Gate Arrays, February 2016.

  106. T. Nguyen, S. Gurumani, K. Rupnow, and D. Chen, “FCUDA-SoC: Platform Integration for Field-Programmable SoC with the CUDA-to-FPGA Compiler,” Proceedings of ACM/SIGDA International Symposium on Field Programmable Gate Arrays, February 2016.

  107. Y-Y Chen, M. Gholipour, and D. Chen, “Flexible Transition Metal Dichalcogenide Field-Effect Transistors: A Circuit-Level Simulation Study of Delay and Power under Bending, Process Variation, and Scaling,” Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, January 2016.

  108. Z. Sun, K. Campbell, W. Zuo, K. Rupnow, S. Gurumani, F. Doucet, and D. Chen, “Designing High-Quality Hardware on a Development Effort Budget: A Study of the Current State of High-Level Synthesis”, Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, January 2016. (Invited)

  109. L. Yang, S. Gurumani, D. Chen, and K. Rupnow, “Behavioral-Level IP Integration in High-Level Synthesis,” Proceedings of International Conference on Field-Programmable Technology, December 2015.

  110. L. Yang, M. Ikram, S. Gurumani, D. Chen, S. Fahmy, and K. Rupnow, “JIT Trace-based Verification for High-Level Synthesis,” Proceedings of International Conference on Field-Programmable Technology, December 2015.

  111. L. Yang, Y. Chen, W, Zuo, T. Nguyen, S. Gurumani, K. Rupnow, and D. Chen, “System-Level Design Solutions: Enabling the IoT Explosion,” Proceedings of IEEE International Conference on ASIC, November 2015. (Invited)

  112. M. Potkonjak, D. Chen, P. Kalla, S. P. Levitan, “DA Vision 2015: From Here to Eternity,” Proceedings of IEEE/ACM International Conference on Computer-Aided Design, November 2015. (Invited)

  113. W. Zuo, W. Kemmerer, J. B. Lim, L.-N. Pochet, A. Ayupoy, T. Kim, K. Han, and D. Chen, “A polyhedral-based SystemC modeling and generation framework for effective low-power design space exploration,” Proceedings of IEEE/ACM International Conference on Computer-Aided Design, November 2015. (Best Paper Award)

  114. Y. Liang, H. Zhu, and D. Chen, “Optimal Blocker Placement for Mitigating the Effects of Geomagnetic Induced Currents Using Branch and Cut Algorithm,” Proceedings of North American Power Symposium (NAPS), October 2015

  115. C. H. Lin, S. Roy, C. Y. Wang, D. Z. Pan, and D. Chen, “CSL: Coordinated and Scalable Logic Synthesis Techniques for Effective NBTI Reduction,” Proceedings of IEEE International Conference on Computer Design, October 2015.

  116. K. Campbell, D. Lin, S. Mitra, and D. Chen, “Hybrid Quick Error Detection (H-QED): Accelerator Validation and Debug using High-Level Synthesis Principles,” Proceedings of IEEE/ACM Design Automation Conference, June 2015.

  117. K. Campbell, P. Vissa, D. Z. Pan, and D. Chen, “High-Level Synthesis of Error Detecting Cores through Low-Cost Modulo-3 Shadow Datapaths,” Proceedings of IEEE/ACM Design Automation Conference, June 2015.

  118. Y.Y. Chen, Z. Sun, and D. Chen “A SPICE Model for Flexible Transition Metal Dichalcogenide Field-Effect Transistors,” Proceedings of IEEE/ACM Design Automation Conference, June 2015.

  119. C. Zhuge, C.W. Lung, D. Chen, and Y.K. Jan, “Development of the Feedback Controlled Indentation System for Assessing Risk of Pressure Ulcers,” Proceedings of Rehabilitation Engineering and Assistive Technology Society of North America (RESNA) Annual Conference, June 2015.

  120. C. Wei, A. Dhar, and D. Chen, "A Scalable and High-Density FPGA Architecture with Multi-Level Phase Change Memory," Proceedings of IEEE/ACM Design, Automation & Test in Europe, March 2015.

  121. A. Ramachandran, Y. Heo, W.M. Hwu, J. Ma, and D. Chen, "FPGA Accelerated DNA Error Correction," Proceedings of IEEE/ACM Design, Automation & Test in Europe, March 2015.

  122. W. Zuo, H. Zheng, S. Gurumani, K. Rupnow, and D. Chen, "New Solutions for System-Level and High-Level Synthesis," Proceedings of IEEE International Symposium on Integrated Circuits, December 2014. (Invited)

  123. S. T. C. Konigsmark, L. Hwang, D. F. Wong, and D. Chen, “System-of-PUFs: Multilevel Security for Embedded Systems,” Proceedings of IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis, October 2014.

  124. Y. Liang and D. Chen, "New Algorithms for Computation Acceleration for Large-scale Smart Grids," Proceedings of IEEE International Conference on Solid-State and Integrated Circuit Technology, October 2014. (Invited)

  125. J. Wang, A. Dhar, D. Chen, Y. Liang, Y. Wang, and B. Guo, "Workload Allocation and Thread Structure Optimization for MapReduce on GPUs," Proceedings of SRC Technical Conference (TECHCON), September 2014.

  126. R. Mancuso, P. Srivastava, D. Chen, and M. Caccamo, "A Hardware Architecture to Deploy Complex Multiprocessor Scheduling Algorithms," Proceedings of IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, August 2014.

  127. Sizhao Li, Shan Lin, Deming Chen, W. Eric Wong, and Donghui Guo, “Analysis of System Reliability for Cache Coherence Scheme in Multi-Processor”, Proceedings of IEEE International Conference on Software Security and Reliability, June 2014.

  128. Y. Liang and D. Chen, "ClusRed: Clustering and Network Reduction-based Probabilistic Optimal Power Flow Analysis for Large-scale Smart Grids," Proceedings of IEEE/ACM Design Automation Conference, June 2014.

  129. C.-H. Lin, L. Wan, and D. Chen, "C-Mine: Data Mining of Logic Common Cases for Low Power Synthesis of Better-Than-Worst-Case Designs," Proceedings of IEEE/ACM Design Automation Conference, June 2014.

  130. S. Gurumani, J. Tolar, Y. Chen, Y. Liang, K. Rupnow, and D. Chen, "Integrated CUDA-to-FPGA Synthesis with Network-on-Chip," Proceedings of IEEE International Symposium on Field-Programmable Custom Computing Machines, May 2014.

  131. M. Gholipour, Y-Y, Chen, A. Sangai, and D. Chen, "Highly Accurate SPICE-Compatible Modeling for Single- and Double-Gate GNRFETs with Studies on Technology Scaling," Proceedings of IEEE/ACM Design, Automation & Test in Europe, March 2014.

  132. H. Zheng, S. Gurumani, K. Rupnow, and D. Chen, "Fast and Effective Placement and Routing Directed High-Level Synthesis for FPGAs," Proceedings of ACM/SIGDA International Symposium on Field Programmable Gate Arrays, February 2014.

  133. Y. Liang and D. Chen, "Fast Large-Scale Optimal Power Flow Analysis for Smart Grid through Network Reduction," Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, January 2014.

  134. S. T. C. Konigsmark, L. Hwang, D. Chen, and D. F. Wong, "CNPUF: A Carbon Nanotube-based Physically Unclonable Function for Secure Low-Energy Hardware Design," ProceediEEE/ACM Asia and South Pacific Design Automation Conference, January 2014.

  135. X. Xie, Y. Liang, G. Sun, and D. Chen, "An Efficient Compiler Framework for Cache Bypassing on GPUs," Proceedings of IEEE/ACM International Conference on Computer-Aided Design, November 2013.

  136. W. Zuo, P. Li, D. Chen, L-N. Pouchet, S. Zhong, and J. Cong, "Improving Polyhedral Code Generation for High-Level Synthesis," Proceedings of IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis, September 2013. (Best Paper Award)

  137. Y-Y. Chen, A. Sangai, M. Gholipour, and D. Chen, "Graphene Nano-Ribbon Field-Effect Transistors as Future Low-Power Devices," Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design, September 2013. (Invited)

  138. H. Zheng, S. Gurumani, L. Yang, D. Chen, K. Rupnow, "High-level Synthesis with Behavioral level Multi-Cycle Path Analysis," Proceedings of IEEE International Conference on Field Programmable Logic and Applications, September, 2013.

  139. Y-Y. Chen, A. Sangai, M. Gholipour, and D. Chen, "Schottky-Barrier-Type Graphene Nano-Ribbon Field-Effect Transistors: A Study on Compact Modeling, Process Variation, and Circuit Performance," Proceedings of IEEE/ACM International Symposium on Nanoscale Architectures, July 2013.

  140. A. Papakonstantinou, D. Chen, W.M. Hwu, J. Cong, and Y. Liang, "Throughput-oriented Kernel Porting onto FPGAs," Proceedings of IEEE/ACM Design Automation Conference, June 2013.

  141. Y-Y. Chen, A. Rogachev, A. Sangai, G. Iannaccone, G. Fiori, and D. Chen, "A SPICE-Compatible Model of Graphene Nano-Ribbon Field-Effect Transistors Enabling Circuit-Level Delay and Power Analysis Under Process Variation," Proceedings of IEEE/ACM Design, Automation & Test in Europe, March 2013.

  142. Y. Liang, H. P. Huynh, K. Rupnow, R. Goh, and D. Chen, "Efficient Concurrent Kernel Execution on GPUs," Proceedings of Workshop on SoCs, Heterogeneous Architectures and Workloads, February, 2013.

  143. W. Zuo, Y. Liang, K. Rupnow, P. Li, D. Chen, and J. Cong, "Improving High Level Synthesis Optimization Opportunity Through Polyhedral Transformations," Proceedings of ACM International Symposium on Field Programmable Gate Arrays, February 2013.

  144. Y. Liang, Z. Cui, K. Rupnow, and D. Chen, "Register and Thread Structure Optimization for GPUs," Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, January 2013.

  145. S. Gurumani, K. Rupnow, Y. Liang, H. Cholakkail, and D. Chen, "High Level Synthesis of Multiple Dependent CUDA Kernels for FPGAs," Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, January 2013. (Invited)

  146. Z. Zhang and D. Chen, "Challenges and Opportunities of ESL Design Automation," Proceedings of IEEE International Conference on Solid-State and Integrated Circuit Technology, October 2012. (Invited)

  147. H. Luo, S. Wei, D. Chen, and D. Guo, "Hybrid Circuit-Switched NOC for Low Cost On-chip Communication," Proceedings of IEEE International Conference on Anti-Counterfeiting, Security and Identification, August 2012.

  148. L. Wan and D. Chen, "CCP: Common Case Promotion for Improved Timing Error Resilience with Energy Efficiency," Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design, July 2012.

  149. W. Huang, Y. Quan, and D. Chen, "Improving Broadcast Efficiency in Wireless Sensor Network Time Synchronization Protocols," Proceedings of IEEE/ACM International Workshop on System Level Interconnect Prediction, June 2012.

  150. S. Zhao, S. Ahmed, Y. Liang, K. Rupnow, D. Chen and D. L. Jones, "A Real-Time 3D Sound Localization System with Miniature Microphone Array for Virtual Reality," Proceedings of IEEE Conference on Industrial Electronics and Applications, July 2012.

  151. Z. Cui, Y. Liang, K. Rupnow, and D. Chen, "An Accurate GPU Performance Model for Effective Control Flow Divergence Optimization," Proceedings of IEEE International Parallel & Distributed Processing Symposium, May 2012.

  152. K. S. Yim, V. Sidea, Z. Kalbarczyk, D. Chen, and R. K. Iyer, "A Fault-Tolerant Programmable Voter for Software-Based N-Modular Redundancy," Proceedings of the IEEE Aerospace Conference, March 2012.

  153. Y. Liang, Z. Cui, S. Zhao, K. Rupnow, Y. Zhang, D. L. Jones, and D. Chen, "Real-time Implementation and Performance Optimization of 3D Sound Localization on GPUs," Proceedings of IEEE/ACM Design, Automation & Test in Europe, Mar. 2012.

  154. K. Rupnow, Y. Liang, Y. Li, D. Min, M. Do, and D. Chen, "High Level Synthesis of Stereo Matching: Productivity, Performance, and Software Constraints," Proceedings of IEEE International Conference on Field-Programmable Technology, December 2011. (Best Paper Nomination)

  155. K. Rupnow, Y. Liang, Y. Li, and D. Chen, "A Study of High-Level Synthesis: Promises and Challenges," Proceedings of IEEE International Conference on ASIC, October 2011. (Invited)

  156. A. Rogachev, L. Wan and D. Chen, "Temperature Aware Statistical Static Timing Analysis," Proceedings of IEEE/ACM International Conference on Computer-Aided Design, November 2011.

  157. A. Papakonstantinou, D. Chen, and W.M. Hwu, "A Code Optimization Framework for Performance Portability of Parallel Kernels Across GPUs and Custom Accelerators", SRC Technical Conference (TECHCON), Sept. 2011.

  158. S. Liu, A. Papakonstantinou, H. Wang, and D. Chen, "Real-time Object Tracking System on FPGAs," Proceedings of Symposium on Application Accelerators in High Performance Computing, July 2011. (Best Paper Award)

  159. C. Dong, C. Chen, S. Mitra, and D. Chen, "Architecture and Performance Evaluation of 3D CMOS-NEM FPGA," Proceedings of IEEE/ACM International Workshop on System Level Interconnect Prediction, June 2011.

  160. A. Papakonstantinou, Y. Liang, J. Stratton, K. Gururaj, D. Chen, W.M. Hwu and J. Cong, "Multilevel Granularity Parallelism Synthesis on FPGAs," Proceedings of IEEE International Symposium on Field-Programmable Custom Computing Machines, May 2011. (Best Paper Award)

  161. C. Peng, C. Dong, and D. Chen, "SETmap: A Soft Error Tolerant Mapping Algorithm for FPGA Designs with Low Power," Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, January 2011.

  162. T. Yan, Q. Ma, S. Chilstedt, D. F. Wong, and D. Chen, "Routing with Graphene Nanoribbons," Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, January 2011.

  163. G. Lucas and D. Chen, "Variation-Aware Layout-Driven Scheduling for Performance Yield Optimization," Proceedings of IEEE/ACM International Conference on Computer-Aided Design, November 2010.

  164. L. Wan and D. Chen, "Analysis of Circuit Dynamic Behavior with Timed Ternary Decision Diagram," Proceedings of IEEE/ACM International Conference on Computer-Aided Design, November 2010.

  165. Q. Dinh, D. Chen, and D.F. Wong, "BDD-Based Circuit Restructuring for Reducing Dynamic Power," Proceedings of IEEE International Conference on Computer Design, October 2010.

  166. Y. Chen, C. Dong, and D. Chen, "Clock Tree Synthesis under Aggressive Buffer Insertion," Proceedings of IEEE/ACM Design Automation Conference, June 2010.

  167. G. Lucas, C. Dong, and D. Chen, "Variation-Aware Placement for FPGAs with Multi-cycle Statistical Timing Analysis", Proceedings of ACM/SIGDA International Symposium on FPGA, February 2010.

  168. Q. Dinh, D. Chen, and D.F. Wong "Dynamic Power Estimation for Deep Submicron Circuits with Process Variation", Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, January 2010.

  169. L. Wan and D. Chen, "DynaTune: Circuit-Level Optimization for Timing Speculation Considering Dynamic Path Behavior", Proceedings of IEEE/ACM International Conference on Computer-Aided Design, November 2009.

  170. C. He, A. Papakonstantinou, and D. Chen, "A Novel SoC Architecture on FPGA for Ultra Fast Face Detection", Proceedings of IEEE International Conference on Computer Design, October 2009.

  171. L. Wan, C. Dong, and D. Chen, "A New Coarse-Grained Reconfigurable Architecture with Fast Data Relay and Its Compilation Flow," Proceedings of Symposium on Application Accelerators in HPC, July 2009.

  172. S. Akram, R. Kumar, and D. Chen, "Workload Adaptive Shared Memory Multicore Processors with Reconfigurable Interconnects," Proceedings of IEEE Symposium on Application Specific Processors, July 2009.

  173. A. Papakonstantinou, K. Gururaj, J. Stratton, D. Chen, J. Cong, and W.M. Hwu, "FCUDA: Enabling Efficient Compilation of CUDA Kernels onto FPGAs," Proceedings of IEEE Symposium on Application Specific Processors, July 2009. (Best Paper Award)

  174. S. Cromar, J. Lee, and D. Chen, "FPGA-Targeted High-Level Binding Algorithm for Power and Area Reduction with Glitch-Estimation," Proceedings of IEEE/ACM Design Automation Conference, July 2009.

  175. C. Dong, S. Chilstedt, and D. Chen, "Variation Aware Routing for Three-Dimensional FPGAs," Proceedings of IEEE Computer Society Annual Symposium on VLSI, May 2009.

  176. C. Dong, S. Chilstedt, and D. Chen, "Reconfigurable Circuit Design with Nanomaterials," Proceedings of Design, Automation and Test in Europe, April 2009. (Invited)

  177. Q. Dinh, D. Chen, and D.F. Wong, "A Routing Approach to Reduce Glitches in Low Power FPGAs," Proceedings of IEEE/ACM International Symposium on Physical Design, March 2009.

  178. C. Dong, S. Chilstedt, and D. Chen, "FPCNA: Field Programmable Carbon Nanotube Array," Proceedings of ACM/SIGDA International Symposium on FPGA, February 2009.

  179. B. Greskamp, L. Wan, R. Karpuzcu, J. Cook, J. Torrellas, D. Chen, and C. Zilles "BlueShift: Designing Processors for Timing Speculation from the Ground Up," Proceedings of IEEE International Symposium on High-Performance Computer Architecture, February 2009.

  180. G. Lucas, S. Cromar, and D. Chen, "FastYield: Variation-Aware, Layout-Driven Simultaneous Binding and Module Selection for Performance Yield Optimization," Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, January 2009. (Best Paper Award)

  181. A. Papakonstantinou, Y. Kifle, G. Lucas, and D. Chen, "MP3 decoding on FPGA: A case study for floating point acceleration," Proceedings of Reconfigurable Systems Summer Institute, Urbana, IL, July 2008.

  182. A. Papakonstantinou, D. Chen, and W.M. Hwu, "Application Acceleration with the Explicitly Parallel Operations System - the EPOS Processor," Proceedings of IEEE Symposium on Application Specific Processors, June 2008.

  183. Q. Dinh, D. Chen, and D.F. Wong, "Efficient ASIP Design for Configurable Processors with Fine-Grained Resource Sharing," Proceedings of ACM/SIGDA International Symposium on FPGA, February 2008.

  184. S. Akram, S. Cromar, G. Lucas, A. Papakonstantinou, and D. Chen, "VEBoC: Variation and Error-Aware Design for Billions of Devices on a Chip," Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, January 2008. (Invited)

  185. C. Dong, D. Chen, S. Haruehanroengra, and W. Wang, "Performance and Power Evaluation of a 3D CMOS/Nanomaterial Reconfigurable Architecture," Proceedings of IEEE/ACM International Conference on Computer-Aided Design, Nov. 2007.

  186. L. Cheng, D. Chen, D.F. Wong, M. Hutton, and J. Govig, "Timing Constraint-driven Technology Mapping for FPGAs Considering False Paths and Multi-Clock Domains," Proceedings of IEEE/ACM International Conference on Computer-Aided Design, Nov. 2007.

  187. Q. Dinh, Y. Bresler, and D. Chen, "Hardware Acceleration for Sparse Fourier Image Reconstruction," Proceedings of IEEE International Conference on ASIC, Oct. 2007. (Invited)

  188. L. Cheng, D. Chen, and D.F. Wong, "GlitchMap: An FPGA Technology Mapper for Low Power Considering Glitches," Proceedings of IEEE/ACM Design Automation Conference, Jun. 2007.

  189. L. Cheng, D. Chen, and D.F. Wong, "DDBDD: Delay-Driven BDD Synthesis for FPGAs," Proceedings of IEEE/ACM Design Automation Conference, Jun. 2007.

  190. D. Chen, J. Cong, Y. Fan and Z. Zhang, "High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs," Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, Jan. 2007.

  191. L. Cheng, L. Deng, D. Chen, and D.F. Wong, "A Fast Simultaneous Input Vector Generation and Gate Replacement Algorithm for Leakage Power Reduction," Proceedings of IEEE/ACM Design Automation Conference, July 2006.

  192. J. Lin, D. Chen, and J. Cong, "Optimal Simultaneous Mapping and Clustering for FPGA Delay Optimization," Proceedings of IEEE/ACM Design Automation Conference, July 2006.

  193. D. Chen, J. Cong, Y. Fan, and J. Xu, "Optimality Study of Resource Binding with Multi-Vdds," Proceedings of IEEE/ACM Design Automation Conference, July 2006.

  194. D. Chen, J. Cong, Y. Fan, G. Han, W. Jiang, and Z. Zhang, "xPilot: A Platform-Based Behavioral Synthesis System," Proceedings of SRC Techcon Conference, October 2005.

  195. D. Chen, J. Cong, and J. Xu, "Optimal Module and Voltage Assignment for Low-Power," Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, Shanghai, China, pp. 850-855, January 2005.

  196. D. Chen and J. Cong, "DAOmap: A Depth-Optimal Area Optimization Mapping Algorithm for FPGA Designs," Proceedings of IEEE/ACM International Conference on Computer-Aided Design, San Jose, California, pp. 752-759, November 2004.

  197. D. Chen and J. Cong, "Delay Optimal Low-Power Circuit Clustering for FPGAs with Dual Supply Voltages," Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design, Newport Beach, California, pp. 70-73, August 2004.

  198. D. Chen, J. Cong, F. Li, and L. He, "Low-Power Technology Mapping for FPGA Architectures with Dual Supply Voltages," Proceedings of ACM International Symposiumon Field-Programmable Gate Arrays, Monterey, California, pp. 109-117, February 2004.

  199. D. Chen and J. Cong, "Register Binding and Port Assignment for Multiplexer Optimization," Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, Yokohama, Japan, pp. 68-73, January 2004.

  200. D. Chen, J. Cong, and Y. Fan, "Low-Power High-Level Synthesis for FPGA Architectures," Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design, Seoul, Korea, pp. 134-139, August 2003.

  201. F. Li, D. Chen, L. He, and J. Cong, "Architecture Evaluation for Power-Efficient FPGAs," Proceedings of ACM International Symposium on Field Programmable Gate Arrays, Monterey, California, pp. 175-184, February 2003.

  202. D. Chen, J. Cong, M. Ercegovac, and Z. Huang, "Performance-Driven Mapping for CPLD Architectures," Proceedings of ACM International Symposium on Field Programmable Gate Arrays, Monterey, California, pp. 39-47, February 2001.

  203. D. Chen, R. Colwell, H. Gelman, P. K. Chrysanthis, and D. Mosse, "A Framework for Experimenting with QoS for Multimedia Services," Proceedings of International Conference on Multimedia Computing and Networking, San Jose, California, January 1996.

Other Workshop Papers, Poster Papers or Online Publications


  1. Meghna Mandava and Deming Chen, “Nimblock: Scheduling for Fine-grained FPGA Sharing through Virtualization,” Poster, ACM/SIGDA International Symposium on Field Programmable Gate Arrays, February 2023.

  2. Xiaofan Zhang, Hanchen Ye, and Deming Chen, “Being-ahead: Benchmarking and Exploring Accelerators for Hardware-Efficient AI Deployment”, MLSys Workshop on Benchmarking Machine Learning Workloads on Emerging Hardware (MLBench21), April 2021.

  3. Hanchen Ye, Cong Hao, Hyunmin Jeong, Jack Huang, and Deming Chen, “ScaleHLS: Achieving Scalable High-Level Synthesis through MLIR”, ASPLOS Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE21), April 2021.

  4. Sitao Huang, Kun Wu, Paul Jeong, Chengyue Wang, Deming Chen, and Wen-mei Hwu, “PyLog: An Algorithm-Centric Python-Based FPGA Programming and Synthesis Flow”, Poster at ACM/SIGDA International Symposium on Field Programmable Gate Arrays, February 2021.

  5. Cong Hao, Xinheng Liu, and Deming Chen, "An FPGA/DNN Co-design Methodology," Poster at SRC TECHCON, September 2019.

  6. Xiaofan Zhang, Hao Cong, Yuhong Li, Yao Chen, Jinjun Xiong, Wen-Mei Hwu and Deming Chen, “A Bi-Directional Co-Design Approach to Enable Deep Learning on IoT Devices,” Joint Workshop on On-Device Machine Learning & Compact Deep Neural Network Representations, ICML 2019 Workshop, June 2019.

  7. Xiaofan Zhang, Mohamed El Hadedy, Wen-mei Hwu, Nam Sung Kim, Jinjun Xiong, and Deming Chen, “Implementing Long-term Recurrent Convolutional Network Using HLS on POWER System,” IBM OpenPOWER Summit, Las Vegas, 2018.

  8. Junsong Wang, Qiuwen Lou, Xiaofan Zhang, Chao Zhu, Yonghua Lin, and Deming Chen, “A Design Flow of Accelerating Hybrid Extremely Low Bit-width Neural Network in Embedded FPGA,” Design Automation Conference (DAC) Late Breaking Results, San Francisco, 2018.

  9. Di He, Boon Pang Lim, Xuesong Yang, Mark Hasegawa-Johnson, and Deming Chen, “Selecting frames for automatic speech recognition based on acoustic landmarks,” The Journal of the Acoustical Society of America, 141(5):3468-3468, DOI: 10.1121/1.4987204, May 2017.

  10. D. Chen, J. Cong, S. Gurumani, W.M. Hwu, K. Rupnow, and Z. Zhang, “System Synthesis and Automated Verification: Design Demands for IoT Devices,” Sensors to Cloud Architectures Workshop, March 2016.

  11. A. Dhar and D. Chen, “Neuromorphic Architecture Inspired Fast, Efficient and Configurable On-Chip Learning Via In-Memory Computing and RRAM”, Poster paper, 2015 Workshop on Hardware and Algorithms for Learning On-a-chip (HALO), Nov. 2015.

  12. Y-Y Chen, A. Sangai, M. Gholipour, and D. Chen, "Effects of Process Variation on the Circuit-Level Performance of Graphene Nano-Ribbon Field-Effect Transistors," Workshop on Variability Modeling and Characterization, November 2013.

  13. K. Rupnow, Y. Liang, D. Min, M. Do and D. Chen, "Mobile 3D Vision - Algorithm and Platform Challenges," FPL 2011 Workshop on Computer Vision on Low-Power Reconfigurable Architectures, 2011.

  14. D. Chen, S. Chilstedt, C. Dong, and E. Pop, "What Everyone Needs to Know about Carbon-Based Nanocircuits," Online Knowledge Center, Topic: Back-End, Sub-topic: New Technologies and Directions, IEEE/ACM Design Automation Conference, 2010. (Invited)

  15. L. Wan and D. Chen, "Circuit Level Dynamic Behavior Analysis through Timed Ternary Decision Diagram," Proceedings of International Workshop on Logic & Synthesis, June 2010.

  16. Z. Zhang and D. Chen, "Challenges and Opportunities of ESL Design Automation", IEEE Electronic Design Processes Symposium, April 2010. (Invited)

  17. A. Papakonstantinou, K. Gururaj, J. Stratton, D. Chen, J. Cong, and W.M. Hwu, "High-Performance CUDA Kernel Execution on FPGAs," International Conference on Supercomputing, June 2009. (Two-page extended abstract.)

  18. C. Dong, S. Chilstedt, and D. Chen, "Variation Aware Routing for Three-Dimensional FPGAs," Workshop on 3D Integration and Interconnect-Centric Architectures, Feb. 2009. (A later version with the same title appeared in IEEE Computer Society Annual Symposium on VLSI, May 2009.)